1. Field of the Invention
The present invention relates to a display device including a circuit formed by using a transistor. In particular, the present invention relates to a display device using an electro-optical element such as a liquid crystal element, a light-emitting element, or the like as a display medium, and an operating method thereof.
2. Description of the Related Art
In recent years, with the increase of large display devices such as liquid crystal televisions, display devices have been actively developed. In particular a technique for forming a pixel circuit and a driver circuit including a shift register or the like (hereinafter also referred to as an internal circuit) over the same insulating substrate by using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon) has been actively developed, because the technique greatly contributes to low power consumption and low cost. The internal circuit formed over the insulating substrate is connected to a controller IC or the like (hereinafter also referred to as an external circuit) through an FPC or the like, and its operation is controlled.
A shift register which is formed by using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous transistors) has been devised among the above-described internal circuits. FIG. 30A shows a structure of a flip-flop included in a conventional shift register (see Reference 1: Japanese Published Patent Application No. 2004-157508). The flip-flop in FIG. 30A includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, a transistor 16, and a transistor 17, and is connected to a signal line 21, a signal line 22, a wiring 23, a signal line 24, a power supply line 25, and a power supply line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. An operating period of the flip-flop in FIG. 30A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in a timing chart in FIG. 30B, and most of the operating period is the non-selection period.
Here, the transistor 12 and the transistor 16 are on in the non-selection period. Thus, since amorphous silicon is used for a semiconductor layer of each of the transistor 12 and the transistor 16, fluctuation in the threshold voltage (Vth) caused by deterioration or the like occurs. More specifically, the threshold voltage rises. That is, since each of the transistor 12 and the transistor 16 cannot be turned on because of rise in the threshold voltage, VSS cannot be supplied to a node 41 and the wiring 23 and the conventional shift register malfunctions.
In order to solve this problem, a shift register in which a threshold voltage shift of the transistor 12 can be suppressed has been devised in Reference 2 (Soo Young Yoon, et al., “Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, pp. 348 to 351), Reference 3 (Binn Kim, et al., “a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1073 to 1076), and Reference 4 (Mindoo Chun, et al., “Integrated Gate Driver Using Highly Stable a-Si TFT's”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1077 to 1080). In Reference 2, Reference 3, and Reference 4, a new transistor (described as a first transistor) is provided in parallel to the transistor 12 (described as a second transistor), and a threshold voltage shift of each of the first transistor and the second transistor is suppressed by inputting inverted signals to a gate electrode of the first transistor and a gate electrode of the second transistor in the non-selection period.
In addition, a shift register in which not only the threshold voltage shift of the transistor 12 but also a threshold voltage shift of the transistor 16 can be suppressed has been devised in Reference 5 (Chun-Ching. et al., “Integrated Gate Driver Circuit Using a-Si TFT”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1023 to 1026). In Reference 5, a new transistor (described as a first transistor) is provided in parallel to the transistor 12 (described as a second transistor), and a new transistor (described as a third transistor) is provided in parallel to the transistor 16 (described as a fourth transistor). Then, a threshold voltage shift of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed by inputting a signal to a gate electrode of the first transistor and an inverted signal to a gate electrode of the second transistor, and inputting a signal to a gate electrode of the third transistor and an inverted signal to a gate electrode of the fourth transistor in the non-selection period.
Further, the threshold voltage shift of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12 in Reference 6 (Young Ho Jang, et al., “A-Si TFT Integrated Gate Driver with AC-Driven Single Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 208 to 211).
Note that each of display devices in Reference 7 (Jin Young Choi, et al., “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 274 to 276) and Reference 8 (Yong Soon Lee, et al., “Advanced TFT-LCD Data Line Reduction Method”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 1083 to 1086), the number of signal lines is reduced to one-third by using a shift register formed using an amorphous silicon transistor as a scan line driver circuit and inputting a video signal to each of subpixels of R, G, and B from one signal line. In each of the display devices in Reference 7 and Reference 8, the number of connections of a display panel and a driver IC is reduced.